A differentiable simulator is only useful if it produces correct physics. Here is how we validate ours, and where we stand today.
Validated against analytical solutions, DEVSIM cross-comparison, and finite-difference gradient checks.
The first line of validation: compare the simulator against analytical solutions from semiconductor physics. A uniformly doped PN junction has well-known analytical I-V characteristics, depletion width vs. voltage, and built-in potential. These are sanity checks that the simulator solves the underlying equations correctly.
| Benchmark | What's Tested | Tests | Tolerance |
|---|---|---|---|
| Shockley Diode Equation | I = I_s (e^(V/nV_t) - 1). Ideality factor n, exponential fit R², rectification ratio, I_s order of magnitude. Tested at 3 doping levels. | 4 | n ∈ [0.8, 2.5], R² > 0.99, rectification > 100x |
| Depletion Width | W = √(2εV_bi(1/N_a + 1/N_d)/q). Symmetric and asymmetric junctions. | 1 | Within max(2 grid cells, 50%) |
| Built-in Voltage | V_bi = V_t ln(N_a N_d / n_i²). Parametrized over 4 doping levels from 10^15 to 10^18 cm^-3. | 1 | < 5% (10% at low doping) |
| MOS Capacitor C-V | Accumulation capacitance near C_ox = ε_ox / t_ox. Depletion C < accumulation C. | 2 | Accumulation C within 5x of C_ox |
| Resistor I-V Linearity | Ohm's law: R² > 0.999 for I-V linearity, resistance within 2x of analytical, current scales with cross-section. | 3 | R² > 0.999, R within 50% |
The most important validation step: compare against an established TCAD solver. We use DEVSIM, an open-source, Python-scriptable finite-volume simulator that solves the same drift-diffusion equations. For each reference device, we build an equivalent structure in both simulators and compare geometry-independent metrics (ideality factor, log-slope, built-in voltage).
Geometry-independent metrics are used because DEVSIM is 1D while Driffusion operates on 2D cross-sections. The physics should agree even if the dimensional representation differs.
| Device | Metrics Compared | Tests | Tolerance |
|---|---|---|---|
| Symmetric PN Diode N_a = N_d = 10^17 cm^-3 |
Ideality factor, log10(I)/V slope | 3 | Ideality within 0.5, slope within 50% |
| Asymmetric PN Diode N_a = 10^16, N_d = 10^18 cm^-3 |
Ideality factor, log10(I)/V slope | 3 | Ideality within 0.5, slope within 50% |
| PIN Diode Near-intrinsic middle region |
Nonzero forward current, V_bi agreement | 2 | V_bi within 10% |
Both live DEVSIM runs (when installed) and pre-computed DEVSIM reference values are used. The reference values were extracted from DEVSIM v2.10.0 on matched device structures.
This is specific to the differentiable approach. The simulator computes gradients via automatic differentiation (AD) through the drift-diffusion solver. If these gradients are wrong, the optimizer might converge but produce physically meaningless device structures.
We verify gradients by comparing AD gradients against finite-difference (FD) approximations. We also verify that the implicit differentiation path (which solves an adjoint system for efficiency) agrees with the unrolled autodiff path (which differentiates through every solver iteration).
| Test Category | What's Verified | Tests | Tolerance |
|---|---|---|---|
| AD vs FD Agreement | Finite-difference gradient check on mobility, doping, and multi-point I-V objectives. Multi-epsilon median for robustness. | 3 | Relative error < 2.0 |
| Implicit vs Unrolled | Implicit differentiation (adjoint) matches unrolled autodiff. Per-channel gradient ratio and cosine similarity. | 2 | Ratio in [0.1, 10], forward Δφ < 10^-6 |
| Gradient Sanity (20x20) | No NaN/Inf, gradient norm in reasonable range, correct sign on mobility perturbation. | 2 | Norm in [10^-3, 10^6], magnitude > 10^-20 |
| ImplantParameterization | FD vs AD on fab-constrained parameterization (dose, energy, mask, type). | 1 | Relative error < 2.0 |
| Multi-Point Objective | FD vs AD through multi-voltage I-V objective (the actual optimization path). | 1 | Relative error < 2.0 |
| Stability & Edge Cases | No NaN at high iteration counts (200+), fallback to unrolled, doping sensitivity, JIT compatibility. | 5 | Relative diff < 0.1, non-zero gradients |
Validated against five independent prior-art works (Hinze & Pinnau 2002, Romano ∂PV 2021, AD-NEGF, DDNet, ChargeTransport.jl). To our knowledge as of 2026-04-26, no commercial or open-source TCAD tool offers exact gradients through a 2D drift-diffusion solver.
Cross-validation against published experimental device data is the next milestone — currently in scoping. The comparison requires finding a published device where the doping profile, geometry, and measured I-V are all fully specified, then reproducing the structure in the simulator and comparing quantitatively.
Beyond the primary validation methods, a comprehensive audit was conducted on the codebase in February 2026, covering current conservation, boundary conditions, solver convergence, parameterization correctness, and optimization-target reachability:
| Category | What's Tested | Tests |
|---|---|---|
| Current Conservation | Anode and cathode currents agree within 1% | 3 |
| Boundary Conditions | Contact BCs enforced correctly | 2 |
| Diode I-V Shape | Forward exponential, reverse saturation, ideality | 3 |
| Grid Convergence | Results converge as grid refines | 2 |
| Solver Convergence | Gummel iteration reaches steady state | 2 |
| Poisson Vacuum Mask | Oxide/vacuum regions handled correctly | 6 |
| Doping Parameterization | Coupled log-doping + type parameterization | 7 |
| Gradient Clipping | Stability under extreme gradient magnitudes | 4 |
| Material Discreteness | Soft material blends discretize correctly | 3 |
| PN Junction Formation | Optimizer discovers spatial doping asymmetry | 4 |
| MOSFET Objective | Ion/Ioff optimization produces gate-modulated structure | 2 |
| Sparse/Dense Agreement | Sparse and dense solver paths produce same results | 2 |
| Built-in Voltage (audit) | V_bi matches analytical formula | 2 |
| Carrier Bounds | Carrier concentrations physically reasonable | 3 |
No simulator captures all physics. Here is what the current version does not model:
| Limitation | Impact | Mitigation |
|---|---|---|
| 2D only | Cannot capture 3D effects (e.g., FINFET wrap-around gate) | Sufficient for planar device validation |
| Constant mobility | Overestimates current at high fields and heavy doping | Field/doping-dependent models planned |
| SRH recombination only | Underestimates recombination in highly doped regions | Auger recombination available but not default |
| No quantum effects | Inaccurate near oxide interfaces at very small dimensions | Acceptable for devices > ~5 nm feature sizes |
| No surface states | Interface charge and trapping not modeled | Affects MOS devices more than PN junctions |
| Isothermal (300K) | No self-heating or temperature gradients | Acceptable for low-power devices |
| DC steady-state only | No transient or AC small-signal analysis | DC I-V is the primary design target |
| Grid-dependent accuracy | Coarse grids (< 10x10) have larger errors | 12x12+ recommended for quantitative work |
| FD gradient tolerance | Finite-difference checks have ~2x tolerance due to numerical noise | Multi-epsilon median reduces false alarms |
All tests can be reproduced locally. The full test suite runs in under 10 minutes on a modern laptop.
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